An MIS transistor structure is useful, for example, as a load device in an inverter or in a static random access memory (SRAM) cell, the latter comprising a pair of cross-connected inverters. Such an MIS structure can be built on a monocrystalline bulk substrate ("bulk" transistor), or it can be built in a polycrystalline semiconductor film located on a dielectric substrate such as glass or quartz ("thin film" transistor or TFT). An array of MIS transistors, especially TFTs, is also useful as access (control) transistors to an array of light emitting areas such as liquid crystal pixels.
A serious problem that arises during circuit operation of MIS transistors, particularly those MIS transistors that are implemented in polycrystalline silicon, stems from high electric fields in the neighborhood of the drain region. These high electric fields are undesirable in the case of polycrystalline thin film transistors because the fields cause undesirably high OFF currents by the mechanism of field emission via crystal grain boundary trapping states. In the case of monocrystalline bulk transistors, these high electric fields generate undesirable hot carriers which cause premature transistor failure. A commonly used remedy for alleviating the effects of high field near the drain is to reduce the maximum field by removing the effective edge of the drain electrode from under the gate, i.e., by separating the edge of the gate and the effective edge of the drain by a setback distance. These techniques are known under the names "lightly doped drain" (for bulk transistors) and "drain offset" (for TFFs). A disadvantage of these techniques is in an unwanted decrease of the source-drain current in the ON state of the transistor, owing to the added series resistance introduced by the lightly doped drain or the drain offset, respectively.